The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device having, for example, an error correcting function.
A memory having an error correcting function, so-called ECC (Error Correcting Code) function, is well known. This type of memory generates a hamming code as a check bit for error correction during a write operation and writes the hamming code into a memory core together with data to be written (hereinafter referred to as the “write data”). During a read operation, this type of memory reads the hamming code from the memory core together with data to be read (hereinafter referred to as the “read data”), detects the location of an error (error bit) in the read data in accordance with the hamming code, and corrects the error. In the subsequent description, ECC-encoded data (i.e., “main data+hamming code”) is referred to as the “ECC data”.
The minimum number of bits of the hamming code is determined by adding the value 1 to the binary logarithm of data bus width. If, for instance, the data bus width is 32 bits, a hamming code of at least 6 bits is required. In this instance, a 1-bit error can be detected and corrected by a 6-bit hamming code. However, a 2-bit error can be merely detected by the 6-bit hamming code. Meanwhile, if a 7-bit hamming code is used in a situation where the data bus width is 32 bits, the 2-bit error can be detected and corrected.
The greater the data bus width, the larger the number of hamming code bits. The ratio between the number of hamming code bits and the data bus width decreases with an increase in the data bus width. Therefore, when the data bus width is increased for a memory having the ECC function and the hamming code is generated for each data, it is possible to reduce the cost of the ECC function.
As such being the case, the data bus width of memories tends to increase. Particularly, the data bus width of a DRAM (Dynamic Random Access Memory) included in an LSI (Large Scale Integration) circuit for an embedded system has a pronounced tendency to increase because it has no interface specification limitations unlike a general-purpose stand-alone memory.
An RMW (Read-Modify-Write) function is incorporated in the aforementioned memory so that write data having a bit width smaller than the data bus width can be written under normal conditions. When the write data has a bit width smaller than the data bus width, the RMW function generates the hamming code and writes it into the memory core after increasing the number of bits to match the data bus width by adding an adequate number of bits (this may be referred to as the “mask bits”) to the data stored in the memory core. The RMW function is disclosed, for instance, in Japanese Unexamined Patent Publication No. 2005-327437.
As described in Japanese Unexamined Patent Publication No. 2005-327437, a memory having the RMW function first reads data (the number of bits is equivalent to the data bus width) at a relevant write address and a hamming code attached to the data from the memory core when writing write data having a bit width smaller than the data bus width. This read operation is called a dummy read.
Next, the ECC data read during the dummy read operation is subjected to ECC decoding. If any error is encountered, it is corrected. Next, bits corresponding to the mask bits of the write data, which are included in the decoded data, are added to the write data to generate a data set (the number of bits is equivalent to the data bus width).
Subsequently, the data set is subjected to ECC encoding for the purpose of generating the hamming code. Next, the ECC data including the data set and the hamming code is written into the memory core.